
`timescale 1 ns / 1 ps

	module NAND_FLASH_Controller_v1_0 #
	(
		// Users to add parameters here

		// User parameters ends
		// Do not modify the parameters beyond this line


		// Parameters of Axi Slave Bus Interface S00_AXI
		parameter integer C_S00_AXI_DATA_WIDTH	= 32,
		parameter integer C_S00_AXI_ADDR_WIDTH	= 5
	)
	(
		// Users to add ports here
		input  		wire 		dll_clk,
		input  		wire 		dclkx2,
		input  		wire 		dclk,
		input  		wire 		rwd_clk,
		input  		wire 		ldpc_clk,
		output 		wire 		F_CEn,
    	output 		wire 		F_WPn,
    	output 		wire 		F_WE,   
    	output 		wire 		F_RE,   
    	output 		wire 		F_CLE,   
    	output 		wire 		F_ALE,  
    	inout  		wire[7:0] 	F_DQ,
    	inout 		wire 		F_DQS,
    	input  		wire 		F_RB,
		output      wire        cclk,
		// User ports ends
		// Do not modify the ports beyond this line


		// Ports of Axi Slave Bus Interface S00_AXI
		input wire  s00_axi_aclk,
		input wire  s00_axi_aresetn,
		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
		input wire [2 : 0] s00_axi_awprot,
		input wire  s00_axi_awvalid,
		output wire  s00_axi_awready,
		input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
		input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
		input wire  s00_axi_wvalid,
		output wire  s00_axi_wready,
		output wire [1 : 0] s00_axi_bresp,
		output wire  s00_axi_bvalid,
		input wire  s00_axi_bready,
		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
		input wire [2 : 0] s00_axi_arprot,
		input wire  s00_axi_arvalid,
		output wire  s00_axi_arready,
		output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
		output wire [1 : 0] s00_axi_rresp,
		output wire  s00_axi_rvalid,
		input wire  s00_axi_rready
	);
// Instantiation of Axi Bus Interface S00_AXI
	wire[7:0] dqi;
	wire[7:0] dqo;
	wire dqoen;
	wire	 dqsi;
	wire	 dqso;
	wire dqsoen;

	assign dqi = F_DQ;
	assign F_DQ = dqoen ? dqo : 8'hz;

	assign dqsi = F_DQS;
	assign F_DQS = dqsoen ? dqso : 1'bz;
	NAND_FLASH_Controller_v1_0_S00_AXI # ( 
		.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
		.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
	) NAND_FLASH_Controller_v1_0_S00_AXI_inst (
		.mclk			(dll_clk),
		.data_clk		(d_clk),
		.data_clkX2		(dclkx2),
		.rw_clk			(rwd_clk),
		.ecc_clk		(ldpc_clk),
		.CEn(F_CEn),
    	.WPn(F_WPn),
    	.WE(F_WE),   
    	.RE(F_RE),   
    	.CLE(F_CLE),   
    	.ALE(F_ALE),  
    	.DQ_i(dqi),
    	.DQ_o(dqo), 
    	.DQ_oen(dqoen), 
    	.DQS_i(dqsi),
    	.DQS_o(dqso),
    	.DQS_oen(dqsoen),
    	.RB(F_RB),
		.S_AXI_ACLK(s00_axi_aclk),
		.S_AXI_ARESETN(s00_axi_aresetn),
		.S_AXI_AWADDR(s00_axi_awaddr),
		.S_AXI_AWPROT(s00_axi_awprot),
		.S_AXI_AWVALID(s00_axi_awvalid),
		.S_AXI_AWREADY(s00_axi_awready),
		.S_AXI_WDATA(s00_axi_wdata),
		.S_AXI_WSTRB(s00_axi_wstrb),
		.S_AXI_WVALID(s00_axi_wvalid),
		.S_AXI_WREADY(s00_axi_wready),
		.S_AXI_BRESP(s00_axi_bresp),
		.S_AXI_BVALID(s00_axi_bvalid),
		.S_AXI_BREADY(s00_axi_bready),
		.S_AXI_ARADDR(s00_axi_araddr),
		.S_AXI_ARPROT(s00_axi_arprot),
		.S_AXI_ARVALID(s00_axi_arvalid),
		.S_AXI_ARREADY(s00_axi_arready),
		.S_AXI_RDATA(s00_axi_rdata),
		.S_AXI_RRESP(s00_axi_rresp),
		.S_AXI_RVALID(s00_axi_rvalid),
		.S_AXI_RREADY(s00_axi_rready)
	);

	// Add user logic here

	// User logic ends

	endmodule
